物理設計工程師（工作地點可選合肥/上海）

Position Description:

Work on physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure. The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation PHY IP physical design, methodology and flow development.

Position Requirement:

Must have BS degree with 5+ years of applicable experience, MS degree with 3+ years of applicable experience in microelectronics, electrical engineering. Essential that the candidate demonstrates strong communication skill. Have demonstrated successful completion of 6+ design projects as an individual contributor. Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues. Solid knowledge on low power design, STA, EMIR/SI analysis, physical verification and DFM. Successful track records on tape out complex advanced node projects. Self motivated and able to work as good individual contributor.

職位描述：? ? ? ? ? ? ?
?物理設計實施工作，包括樓層規(guī)劃、電網(wǎng)設計、地點和路線、時鐘樹合成、定時關閉、電源/信號完整性簽署、物理驗證（DRC/LVS/天線）、EM/IR簽署、DFM關閉。候選人將有機會從事多種具有挑戰(zhàn)性的設計，即低功耗和高速設計。職責包括參與或領導下一代PHY IP物理設計、方法和流程開發(fā)。
職位要求：? ? ? ? ? ? ??
必須具有理學學士學位，5年以上相關工作經(jīng)驗，理學碩士學位，3年以上微電子、電氣工程相關工作經(jīng)驗。應聘者必須具備很強的溝通能力。以個人貢獻者的身份成功完成了6個以上的設計項目。有ASIC設計流程、分層物理設計策略和方法的經(jīng)驗，了解深亞微米技術問題。扎實的低功耗設計、STA、EMI/SI分析、物理驗證和DFM知識。在磁帶輸出復雜的高級節(jié)點項目上成功跟蹤記錄。自我激勵，能夠作為優(yōu)秀的個人貢獻者工作。