驗證工程師（工作地點可選合肥/上海）

Position Description:?

Deliver and implement advanced verification solution by utilizing Synopsys Verification product portfolio. The engineers need to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies. Specific responsibilities include: Deep understanding on ASIC design and verification flow. Excellent knowledge of advanced verification methodology. Good in System Verilog, System C and using Verification components (VIP). Experienced on developing and using assertion based verification and formal analysis method. Skilled in scripting language like Perl, C shell, Python, Makefile.

Position Requirement:

Must have BS degree with 5+ years of applicable experience, MS degree with 3+ years of applicable experience in microelectronics, electrical engineering. Essential that the candidate demonstrates strong communication skill. Have demonstrated successful completion of 6+ design projects as an individual contributor. Demonstrated hands on experience and expertise with EDA verification tools, flow and methodologies required to execute verification projects. Need to demonstrate successful completion of 3+ verification projects as individual contributor. Memory IP project verification experience is preferred.

職位描述：? ? ? ? ? ? ??
DELIVER和實施先進的驗證方案驗證城市利用Synopsys公司的產(chǎn)品組合?！豆こ處熜枰男袨樽鳛橐粋€強大的團隊成員和contributor。法院判決的一般定義在運動實踐和政策。具體責任包括：深的理解在ASIC設計和驗證流程。優(yōu)秀大學的先進知識的驗證方法。好的Verilog的系統(tǒng)，系統(tǒng)采用C和核查零件（VIP）。治療對開發(fā)和利用assertion推理和分析方法驗證的目的。在skilled腳本語言像Perl，Python，C殼，makefile。
職位要求：? ? ? ? ? ? ??
必須具有理學學士學位，5年以上相關(guān)工作經(jīng)驗，理學碩士學位，3年以上微電子、電氣工程相關(guān)工作經(jīng)驗。應聘者必須具備很強的溝通能力。以個人貢獻者的身份成功完成了6個以上的設計項目。在執(zhí)行驗證項目所需的EDA驗證工具、流程和方法方面具有實踐經(jīng)驗和專業(yè)知識。需要證明作為個人貢獻者成功完成了3+個驗證項目。有內(nèi)存IP項目驗證經(jīng)驗者優(yōu)先。