Focus on high speed interface IP design/implementation. The engineers need to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies. Specific responsibility include: Proficiency in logic design, simulation Proficiency in Verilog and simulation environment. Good knowledge of IC design. At least five year experience working on digital IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.
Position Requirement:
Must have BS degree with 5+ years of applicable experience, MS degree with 3+ years of applicable experience in microelectronics, electrical engineering. Essential that the candidate demonstrates strong communication skill. Have demonstrated successful completion of 6+ design projects as an individual contributor. Familiar with one or more interface IP protocol including JEDEC-DDR, HBM, PCIE, USB, GDDR6 etc. and have memory IP project design experience is preferred.
